Approximate Computing Circuits for Energy-Efficient Signal Processing

01 Jul 2014

Maintaining the notion that a computer always produces a perfect result is often unnecessarily expensive. In many application domains, such as digital signal processing (DSP), inherent notions of signal quality set, for example, by quantization and compression artifacts allow for small additional reductions in output quality to be traded off for significant energy gains. WNCG Prof. Andreas Gerstlauer and students, in collaboration with UT Austin Electrical and Computer Engineering Prof. Michael Orshansky focus on hardware approximations at the basic circuit and logic levels.

Recognizing that traditional worst-case operation is suboptimal from an energy point of view, the UT Austin team developed strategies that aim to accept, in a systematically controller manner, a small amount of low probability timing errors in exchange for large energy savings under aggressively reduced supply voltages. By exploiting algorithm, hardware, and input characteristics to minimize error probability and magnitude, and by applying novel low-energy post-processing techniques, the research team shows that up to 50% energy savings are possible while maintaining a good output quality in typical image, video, and audio processing kernels, such as (I)DCTs and digital filters.

More recently, the UT Austin team has explored quality-energy (Q-E) optimal structures for basic arithmetic building blocks, such as adders and multipliers that do not rely on voltage scaling but instead produce an approximate output at reduced complexity and produce energy by directly modifying the Boolean logic of the circuit. This led to the development of algorithms and tools for synthesis of general approximate logic circuits under arbitrary error magnitude and frequency constraints. Ongoing work is concerned with expanding the scope of approximate hardware synthesis towards high-level synthesis and compilation of complete application kernels into approximate hardware or software processors.

This research is funded by the National Science Foundation and Intel. 

Paper 1: Muti-Level Approximate Logic Synthesis under General Error Constraints

Paper 2: Modeling and Synthesis of Quality-Energy Optimal Approximate Adders

Paper 3: Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-based Systems