Host-Compiled Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation of Multi-Processor-Systems-on-Chip

Simulations remain one of the primary mechanisms for early validation and exploration of systems with complex dynamic interactions, such as typical multi-processor systems-on-chip (MPSoCs). With ever increasing complexities, traditional approaches based on register transfer level (RTL) or instruction-set simulation (ISS) are often either too slow or too inaccurate, especially in multi-core and multi-processor contexts.

Prof. Andreas Gerstlauer and his students and collaborators have developed so-called host-compiled simulators as ISS alternatives. In such approaches, hardware and software is modeled at a functional C code source level, which results in fast native simulation of application functionality. For accuracy, source code is back-annotated with target metrics. The WNCG team developed approaches for automatic back-annotation of source-level application code with both timing and energy estimates that allow for power and performance simulations with more than 99% accuracy, compared to a cycle-accurate model, all while running in close to native simulation speeds of more than 1000MIPS. In recent work, the research team extended this approach towards capturing, modeling and simulating a full range of performance, energy, power, reliability and thermal (PERPT) metrics at similar speeds and accuracies.

Back-annotated source code is then further wrapped into lightweight models of operating systems (OSs) and processor hardware that integrate into standard transaction-level modeling (TLM) backplanes to provide a complete host-compiled multi-core system simulator. This includes emulation of the complete software execution environment as well as co-simulation with other system components. Within the context of such discrete-event simulations of concurrent system behavior, the granularity of the simulated model in traditional approaches determines a fundamental tradeoff between speed and accuracy, where Prof. Gerstlauer's group have been able to show that errors can potentially become unbounded, which is a serious problem for real-time system evaluation. To overcome this problem, the group developed integrated modeling solutions that can automatically adjust timing granularities to optimally navigate speed and accuracy tradeoffs, including fast and accurate simulation of cache behavior. With this, full-system simulations at the speed of a coarse-grain model (in excess of 900MIPS) but with fine-grain accuracy (of more than 90%) are possible. The WNCG team is currently extending this approach to incorporate interactions with other components and shared caches equally managed by the host-compiled OS and processor models. 

This research is funded by the Semiconductor Research Corporation (SRC). 

Paper 1: Host-Compiled Multi-Core System Simulation for Early Real-Time Performance Evaluation

Paper 2: FastSpot: Host-Compiled Thermal Estimation for Early Design Space Exploration

Paper 3: Automated, Retargetable Back-Annotation for Host-Compiled Performance and Power Modeling

Paper 4: Dynamic Power and Performance Back-Annotation for Fast and Accurate Functional Hardware Simulation