Quality-Energy Aware Synthesis of Approximate Hardware

Approximate computing is an aggressive design technique aimed at achieving significant energy savings by trading off computational precision and accuracy in inherently error-tolerant applications. This introduces a new notion of quality as a fundamental design parameter. While ad-hoc solutions have been explored at various levels, systematic design approaches are lacking. In this work, we investigate quality-energy (Q-E) aware compilation and synthesis of high-level application models into approximate software or hardware. Building on earlier work on the design of approximate digital logic and arithmetic units, such as basic adders and multipliers, we optimally determine accuracy levels in individual operations across a complete program such that energy is minimized while a specified, statistical output quality constraint is met. Results show that our analysis and optimization framework can track min/max, statistical inequality or variance based quality metrics, such as (P)SNR with high accuracy. Corresponding Q-E optimizations have been integrated into standard high-level, C-to-RTL hardware synthesis flows. With this, it becomes possible to automatically generate a range of accuracy-scalable hardware accelerators that achieve significant energy reductions of up to 65% while guaranteeing controlled degradations in output quality.

Relevant reference: Seogoo Lee and Andreas Gerstlauer, "Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems," chapter in an upcoming Springer Book (preprint available).